With the increasing downscaling of integrated circuits and increasingly higher requirements for integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFETs) were thus developed. FIGS. 1 and 2 illustrate perspective views of conventional FinFETs. Fins 104 are formed as vertical silicon fins extending above substrate 102, and are used to form source and drain regions 106 and channel regions therebetween (not shown). Vertical gates 108 intersect the channel regions of fins 104. While not shown in FIGS. 1 and 2, gate dielectrics are formed to separate the channel regions from the respective vertical gates 108. The ends of fins 104 receive source and drain doping implants that make these portions of fins 104 conductive.
The structure shown in FIG. 1 is a silicon-on-insulator (SOI) FinFET structure, which is formed using an SOI substrate including semiconductor substrate 102, buried oxide layer (BOX) 110, and an overlying silicon layer. The overlying silicon layer is patterned to form fin 104, on which the FinFET device is based. SOI FinFET devices have excellent electrical performance. However, the manufacturing cost is high.
The structure shown in FIG. 2 is a bulk FinFET structure, which is formed starting from a bulk silicon substrate 102. The manufacturing cost of the bulk FinFETs is lower compared to SOI FinFETs. However, punch-through currents (leakage currents) may flow in a region not controlled by gate 108, as shown as the region 112 in FIG. 3, which is a cross-sectional view of the structure shown in FIG. 2. The cross-sectional view is made through a plane crossing line A-A′ in FIG. 2. Conventionally, to reduce the punch-through currents, an impurity implantation is performed using a high energy to dope region 112 to a high impurity concentration, for example, about 1019/cm3, wherein the impurity has a conductivity type opposite to that of source/drain regions 106. The implantation is performed after the formation of fin 104, but before the formation of gate 108. The entire fin 104 is thus implanted. By using this method with a high impurity concentration, although the punch-through currents are reduced, the carrier mobility is adversely reduced. Additionally, in this structure the fin height is affected by the position of the top surface of STI region 110, which position is varied in the multiple cleaning processes performed in subsequent manufacturing processes. The fin height variation is thus high, resulting in a device performance variation.
Besides the above-discussed issues, on a same semiconductor chip, FinFETs having different fin heights may be needed. FIGS. 4 and 5 illustrate conventional dual-fin-height structures. Referring to FIG. 4, on silicon substrate 200, fins 202 and 204 are formed with the same heights. Dielectric layer 206 is then formed over silicon substrate 200. Dielectric layer 206 is recessed by different recessing depths, so that the exposed portions of fins 202 and 204 have different heights. The exposed portions of fins 202 and 204 are then used to form FinFETs. The structure as shown in FIG. 4 also suffers from the fin-height variation problem and the degraded carrier mobility due to the requirement for heavily doping the fins in order to reduce leakage currents. Further, in the subsequent gate-etching step, residues of the gate electrode layer may be undesirable left un-etched, causing circuit failure.
FIG. 5, on the other hand, illustrates a dual-fin-height structure formed on a silicon-on-insulator (SOI) substrate including buried oxide layer 210 on silicon substrate 200. The different heights of fins 212 and 214 may be achieved by oxidizing a top portion of fin 212, and removing the resulting oxide. Such formation methods, however, may result in undesired tapered gates in the resulting FinFETs. In addition, the SOI wafers are highly priced.
What is needed in the art, therefore, is formation methods and structures thereof that incorporate FinFETs to take advantage of the benefits associated with the increased drive currents while at the same time overcoming the deficiencies of the prior art.